This invention relates to wiring of a data bus and, in particular, wire structure of a data bus on a motherboard and a memory module board plugged into a connector on the motherboard. Typically, a personal computer includes a motherboard and memory module boards.
In recent years, the processing speed of a CPU (central processing unit) has accelerated, and as a result, it is required that the frequency response of a data bus becomes faster. In this specification, it is assumed that the frequency response of a data bus is over 100 MHz.
In a conventional data bus of a personal computer, the T-stub wiring structure shown in FIG. 1 is adopted for branching bus lines and control lines for DRAM (dynamic random-access memory). The following describes a memory module 80 with the T-stub wiring structure with reference to FIG. 1.
A connector 83 is installed on a bus line 82 wired on a main board 81. A memory module board 84 is plugged into the connector 83. One end of a line 86 on the memory module board 84 is connected with the bus line 82 at a contact 85. This connection forms an inverted letter “T” on FIG. 1. The other end of the line 86 is connected with a lead pin 88 of a DRAM chip 87. Thus the line 86 is branched out from the bus line 82 at the connector 83 to form the letter “T”.
The T-stub wiring structure causes limitation of signal transmission in the memory module 80. Therefore, for example, if the control clock of the memory module 80 is about 100 MHz, then the maximum number of the memory module 80 that can be connected with the bus line 82 is about four. If the control clock is over 133 MHz, then the maximum number is about 2. The maximum data rate that can be read or written through the bus line 82 is about 20 Mbps/pin.
In the Japanese unexamined patent publication number H11-251539, namely 251539/1999, another memory module 90 is disclosed as shown in FIG. 2. On one hand in the memory module 80, the bus line 82 is continuously wired on the main board 81. The section between opposite contacts of the connector 83 on the main board 81 is wired the bus line 82. On the other hand, in the memory module 90, a bus line 92 is divided between opposite contacts of a connector 93 on a main board 91. Instead, a through line 99 is wired from one side to the other side of a memory module board 94. Thus, in the memory module 90, one wiring pass via a contact 95, a line 96 and a lead pin 98 forms a stub wiring structure, and another wiring pass via the bus line 92, the connector 93, a contact 95, the through line 99, a contact 95, the connector 93 and the bus line 92 forms a stubless wiring structure.
According to the Japanese unexamined patent publication No. H11-251539, it is said that the memory module 90 has less signal reflection or signal distortion caused by incoordination of impedance in a stub wiring structure than the memory module 80.
The Japanese Unexamined Patent Publication (JP-A) Number 2001-257018 discloses another memory module 100 as shown in FIG. 3.
Compared with FIG. 2, in the memory module 100, a through line 109 is wired at a different position on a memory module board 104. In the memory module 90, the through line 99 is wired so as to connect contacts 93 on both side with each other. On the other hand, in the memory module 100, the through line 109 is wired at the position where a lead pin 108 is connected to a line 106.
In the memory module 100, only the lead pin 108 is stub-wired. The rest of the wiring pass has a stubless wiring structure. Therefore, the memory module 100 has less incoordination of impedance caused by a stub wiring structure than the memory module 90. As a result, in the memory module 100, less signal reflection and signal distortion occur than in the memory module 90.
When a DRAM chip is connected to a bus line, the input capacitance of the DRAM chip causes additional capacitance to the bus line. Additional capacitance causes incoordination of impedance around the DRAM chip. The incoordination of impedance causes signal reflection and, exercises a harmful influence on frequency response of the data bus. In the memory modules 80, 90 and 100, however, the incoordination of impedance around the DRAM chip is not taken into consideration.
It is one object of the present invention to provide a data bus structure that can avoid harmful influence caused by additional capacitance of an integrated circuit such as a DRAM chip on the data bus.